**Fault-Tolerant Design of a Magnetic Bearing Digital Controller Based on Dual DSP** Home > Bearing Knowledge > Fault-Tolerant Design of a Magnetic Bearing Digital Controller Based on Dual DSP *728*90 created on 2018/5/16* var cpro_id = "u3440131";

Fault-Tolerant Design of a Magnetic Bearing Digital Controller Based on Dual DSP

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**Introduction** Electromagnetic bearings (AMB) are advanced high-performance bearings that use controllable electromagnetic force to suspend the rotor. They offer numerous advantages, such as no mechanical contact, high speed, high precision, and no need for lubrication or sealing. These features make them ideal for high-tech applications like aerospace, ultra-high-speed machining, and precision manufacturing. Because the magnetic suspension system is inherently unstable, the performance of the control system directly affects the functionality of the magnetic bearing. In recent years, digital control has developed rapidly both domestically and internationally, and digital controllers are becoming the mainstream in future magnetic bearing systems. This article focuses on industrial application requirements and cost considerations. It introduces a dual-DSP fault-tolerant control scheme, as shown in the dotted box in Figure 1. The design addresses sensor, coil, and amplifier faults but does not cover all aspects in detail. Fault tolerance is essential for ensuring reliability in magnetic bearing systems. Given the limited time and program space margins in a digital signal processor (DSP)-based control system, hardware redundancy—specifically multi-DSP redundancy—is used to enhance system reliability. In a multi-DSP redundant system, the key challenges include reconfiguration strategies, switching logic, and synchronization. Small-scale terminal systems require efficient control with minimal resources. This paper proposes a dual-DSP hot-standby redundant control system to meet these needs while maintaining cost-effectiveness. **Design Principle** The control system layout is shown in Figure 2. Redundant intermediate control functions are implemented using a CPLD. Analog signals are input to two DSPs, and the main DSP is selected by an intermediate control module. The main DSP processes the data, converts it to analog output, and sends timing and RS-232 signals. An input buffer module reduces the impact of input impedance, while a first-order buffer minimizes interference from peripheral circuits. The system includes buffering for RS-232, crystal, reset, and external abort signals. Analog signals are matched using voltage followers, reducing error and A/D conversion time. DSP clock synchronization ensures that the dual-DSP system operates in sync. A crystal signal is used for synchronization. During operation, the power supply must stabilize, and the crystal oscillator must fully oscillate before resetting the DSP. Testing showed that stabilization takes about 40ms, so the reset time should be longer than that. A Schmitt trigger is added after reset to improve noise immunity. A hardware fault detection module uses the CLKOUT pin of each DSP as a basis for detecting hardware faults. If CLKOUT outputs a stable waveform, the DSP is considered normal. If no waveform is detected, the intermediate control module blocks the faulty DSP. The output bus voting module compares the output signals of the two DSPs. If they differ, it indicates a soft fault, and the system stops the faulty output. The intermediate control module then handles the situation, enabling fault tolerance. Only the upper 8 bits of the output data are voted on to account for A/D conversion errors. The intermediate control module evaluates the output from the bus voting and hardware fault modules to determine the main DSP. The main DSP controls external outputs, including D/A conversion and RS-232 signals. The intermediate control module's decision-making process involves checking both hardware and software modules. If both are normal, DSP1 is selected as the main. If a hardware fault occurs, the faulty DSP is blocked, and an alarm is triggered. If both fail, the system initiates a safety protocol. If only a software error occurs, the system resets, and the number of resets is tracked. If resets exceed four times without a correct output, the security system is activated. The DSP software flow diagram (Figure 3) shows how the watchdog module monitors the system. After a reset, the watchdog checks the reset flag. If it detects a watchdog reset, it triggers an output bus error. Otherwise, it performs an online self-test. If the test fails, the CPLD blocks the hardware. To minimize the impact of resets, double-port RAM (IDT7133) stores temporary data, allowing rapid recovery. Online self-tests are controlled by the CPLD, comparing real-time results with stored offline data. If they match, the system passes; otherwise, the faulty DSP is blocked. The reliability of the intermediate control module, implemented via CPLD, is much higher than that of a DSP-based system. The probability of failure in the CPLD is nearly zero, and its uniformity time far exceeds that of a DSP. According to the electronic system model, the reliability of a single unit follows an exponential distribution: Ri(t) = e^(-λt), where λ is the failure rate. The mean time between failures (MTBF) is 1/λ. For a dual-DSP system, the MTBF increases by 1.5 times, significantly improving the reliability of the manipulator system. **Conclusion** This paper presents a fault-tolerant design for a magnetic bearing digital controller using dual DSPs. The system integrates hardware and software fault detection, enhancing overall reliability and providing robust support for industrial applications of magnetic bearings.

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